In some situation it is advantages or
even necessary to use the same conductor for communication and
delivery as the presented in Illustration 1.
Power and data can be delivered together, through the 2-wire bus simultaneously, but data and power must not affect each other. To address this requirement, it is necessary to block data and power from each other on the same bus when they are present at the same time. The active data signal is an AC signal and power is a DC signal, obviously the capacitor can be used to block the power and the inductor can be used to block the AC signal.
where C tens μF level and where L tens mH level
The inductance value L is required as large as possible to provide a very high impedance to the AC signals. The value of the inductor should be big enough (like tens mH level), and if necessary, continue using coupling inductor to increase inductance of each.
High-level data link control (HDLC) is one of the most enduring and fundamental standards in communications. HDLC fulfills Level 2 of the Open System Interconnect (OSI) model of communications. It includes an 8-bit begin-frame flag, a 16-bit address, an 8- or 16-bit control field, variable-length payload data, a 16- or 32-bit cyclic-redundancy-check (CRC) field, and an 8-bit end-of-frame flag. HDLC is specified in the ISO/IEC 3309 standard. It provides a convenient method of transporting packet information through a network, whether it's by x.25 transactions, Switch Virtual Circuits (SVCs) in frame relay, ISDN D-channel, call setup in a cellular base-station, or Internet Protocol (IP) on xDSL transport.
High Level data Link (HDLC) is serial communication like provide high speed connection solution on single wire for each communication side and clock, support point to point communication and point to multi point solution (multi drop), HDLC provides very low cost solution for inter connection communication applications
The HDLC is a bit-oriented protocol with the serial transmission data encapsulated by 01111110 flags. An HDLC frame is composed of the flag and the serial transmission data. There are five fields in an HDLC frame: flag, address, control, information (variable length), and FCS. The FCS is calculated according to the CRC error detecting scheme from the serial bit stream of the address, control, and information fields. It is usually a 16-bit or 32-bit pattern used for checking the frame data integrity.
In addition to separating the serial transmission data, the HDLC flag can also be used to fill the time gap when there is no data to be transferred. Figure shows the HDLC frame format and the typical HDLC bit stream.
For HDLC modes supports the use of opening and closing message flags. The 7Eh (01111110b) flag is the opening and closing flag. An HDLC message is always bounded by this flag at the beginning and the end of the message.
It is configured to calculate and insert either a 16- or 32-bit Frame Check Sequence (FCS) for HDLC packets, provided the packet length contains a minimum of 2 octets. The FCS is always calculated over the entire packet length.
For all HDLC modes that require FCS calculation, the polynomials used to calculate FCS are according to ITU-T Q.921 and ISO 3309-1984.
• CRC-16: x16 + x12 + x5 + 1
• CRC-CCITT = x16 + x12 + x5 + 1
• CRC-32: x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
Seven consecutive 1s constitute an abort code. Receiving the abort code causes the current frame processing to be aborted and further data transfer into shared memory for that message is terminated. After detecting the abort code, it enters a scan mode, which searches for a new opening flag character.
In some cases when there is a priority issue or a problem on the data link, the transmitter may want to abandon the transmission of the current HDLC frame before it is fully transmitted. This is done by asserting the abort sequence, at least seven but fewer than 15 consecutive 1's. If the number of 1's is more than 15, it will be recognized as an idle sequence. Instead of transmitting consecutive back-to-back flags, an idle sequence can also be used when no data needs to be transferred. However, the idle sequence is usually used to support half-duplex operation. When the idle sequence is received, the transmission direction will be reversed. The half-duplex operation is not supported in this design.
The HDLC provides zero-bit insertion and deletion when it encounters five consecutive 1s within a frame. In the receiver, the zero-bit is removed (discarded). In the transmitter, the zero-bit is inserted after each sequence of five 1s.
The flag pattern, 011111110, is also a possible sequence in other HDLC fields. In order to make the flag unique to the whole bit stream, a zero insertion and deletion technique is applied to the nonflag fields. For data transmission, whenever there are five consecutive 1's being transmitted, an additional redundant zero bit will be inserted immediately after the five 1's. This is called “zero insertion” or “zero stuffing”. When receiving data, whenever there are five consecutive 1's followed by a zero, the zero will be ignored. This is called “zero deletion” or “zero unstuffing”.
module implements all the required HDLC receiver functions
including flag detection, zero unstuffing, abort detection,
checking. The block diagram of this module is shown in Figure.
Once the F_DETECT sub-module detects the HDLC flag, after eight RxClk clocks, the Z_UNSTUFF and A_DETECT sub-modules will be enabled for zero unstuffing and abort detection respectively. Once enabled, the Z_UNSTUFF sub-module will keep track of the incoming bit stream and disable the downstream logic for one clock if a zero bit is followed by five consecutive 1's. So, the zero bit inserted to make the 01111110 flag unique will be unstuffed from the bit stream. The original data without zero bits insertion will then be shifted into the R_SHIFT sub-module. The RxOutputData[7:0] bus will output the R_SHIFT data value once eight bits of data are collected. When this happens, the RxDataWrite_n signal will be asserted for one RxClk clock period to indicate that to the external memory. The FCS data at the end of the receiving HDLC frame will also be transmitted through the RxOutputData[7:0] bus with RxDataWrite_n asserted.
The BIT_CNT and CRC_CHK sub-modules are used for detecting the error of the receiving HDLC frame. The BIT_CNT sub-module will report the octet error if the total number of bits received after zero unstuffing is not a multiple of eight (i.e. mis-aligned byte count). The CRC-CHK sub-module will check the FCS field to see if there is a CRC error. The RxOutputData[7:0] bus will output these results along with the result of the abort detection. This status will be reported after the entire HDLC frame is received or the abort is detected. The RxStatusWrite_n signal will be asserted for one RxClk clock period to indicate that the value present on RxOutputData[7:0] is the status instead of the data. The bit assignment of this status byte is shown in Figure.
The HDLC module contains a digital phase-locked loop (DPLL) function to recover clock information from a data stream with NRZI or FM encoding. The DPLL is driven by a clock that is normally 32 (NRZI) or 16 (Manchester) times the data rate. The DPLL uses this clock, along with the data stream, to construct the clock.
the FM mode, the DPLL clock must be 16 times the data rate.
counter in the DPLL counts from 0 to 31,
so the DPLL makes two sampling clocks during the 0 to 31
cycle. The DPLL output is Low while the DPLL
is waiting for an edge in the incoming data stream. The first
the DPLL detects is assumed to be a valid
clock edge. From this point, the DPLL begins to generate
module implements all the required HDLC transmission
functions such as flag insertion, zero stuffing, abort
and FCS generation for CRC check. The block diagram of this
original data XOR clock = Manchester value
Level). Manchester (bi-phase level) encoding always produces a
transitionat the center of the
bit cell. If the transition is Low to High, the bit is 0. If the
transition is High to Low, the bit is 1.
Encoding of Manchester format requires an external circuit
of a ‘D’flip-flop and four
The channel of the RS-485 contains a digital phase-locked loop that can be used to recover clock information from a data stream with Manchester encoding. The DPLL is driven by a clock nominally at 16 times the data rate.
The basic structure of all-digital phase-locked loop (DPLL) as shown below. Mainly by DPD (digital phase detector), DLF (digital loop filter), DCO (digitally controlled oscillator) three parts. DPLL is a phase-feedback control systems. It will transmit phase error, between input signal data_in and local recovery clock clk_dpd, into the DLF, the pairs of phase error signal smoothing filter, and generates control signals control the DCO movement. DCO according to control signal given instructions to regulate the internal high-speed oscillator oscillation frequency. Through the continuous feedback regulation, the phase of the output clock clk_dpd to track the phase of the input data data_in.
A simple VHDL module, which performs Manchester decoding and clock recovery, has been developed. The main function of the module is to receive a Manchester encoded signal, decode it and extract clock signal from it. The module generates two clock signals – one of the same frequency as the input Manchester signal, the other one of a doubled frequency. Also, the module provides decoded data bits in series on one of its outputs. Each of the data bits can be received by some other module on the falling edges of the generated clock signal.
The general structure: